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IS61LF25636A Datasheet(PDF) 19 Page - Integrated Silicon Solution, Inc |
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IS61LF25636A Datasheet(HTML) 19 Page - Integrated Silicon Solution, Inc |
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19 / 32 page  Integrated Silicon Solution, Inc. — 1-800-379-4774 19 Rev. A 05/04/05 ISSI® IS61LF25636A IS61LF51218A IS61VF25636A IS61VF51218A IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61LF/VF25636A and IS61LF/VF51218A have a serial boundary scan Test Access Port (TAP) in the PBGA package only. This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC stan- dard 2.5V I/O logic levels. DISABLING THE JTAG FEATURE The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the de- vice will start in a reset state which will not interfere with the device operation. TEST ACCESS PORT (TAP) - TEST CLOCK The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. TEST MODE SELECT (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. TEST DATA-IN (TDI) The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 Bypass Register Instruction Register Identification Register Boundary Scan Register* TAP CONTROLLER Selection Circuitry Selection Circuitry TDO TDI TCK TMS TAP CONTROLLER BLOCK DIAGRAM |
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