16

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

08/11/05

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A

IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

6.5

7.5

Symbol

Parameter

Min.

Max.

Min. Max.

Unit

fmax

Clock Frequency

—

133

—

117

MHz

Cycle Time

7.5

—

8.5

—

ns

Clock High Time

2.2

—

2.5

—

ns

Clock Low Time

2.2

—

2.5

—

ns

Clock Access Time

—

6.5

—

7.5

ns

Clock High to Output Invalid

2.5

—

2.5

—

ns

Clock High to Output Low-Z

2.5

—

2.5

—

ns

Clock High to Output High-Z

—

3.8

—

4.0

ns

Output Enable to Output Valid

—

3.2

—

3.4

ns

Output Enable to Output Invalid

2.5

—

2.5

—

ns

Output Enable to Output Low-Z

0

—

0

—

ns

Output Disable to Output High-Z

—

3.5

—

3.5

ns

Address Setup Time

1.5

—

1.5

—

ns

Read/Write Setup Time

1.5

—

1.5

—

ns

Chip Enable Setup Time

1.5

—

1.5

—

ns

Address Advance Setup Time

1.5

—

1.5

—

ns

Data Setup Time

1.5

—

1.5

—

ns

Address Hold Time

0.5

—

0.5

—

ns

Write Hold Time

0.5

—

0.5

—

ns

Chip Enable Hold Time

0.5

—

0.5

—

ns

Address Advance Hold Time

0.5

—

0.5

—

ns

Data Hold Time

0.5

—

0.5

—

ns

ZZ High to Power Down

—

2

—

2

cyc

ZZ Low to Power Down

—

2

—

2

cyc

Notes:

1. Configuration signal MODE is static and must not change during normal operation.

2. Guaranteed but not 100% tested. This parameter is periodically sampled.

3. Tested with load in Figure 2.