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IS61LF12832A Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc |
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IS61LF12832A Datasheet(HTML) 11 Page - Integrated Silicon Solution, Inc |
11 / 25 page ![]() Integrated Silicon Solution, Inc. — 1-800-379-4774 11 Rev. 00A 08/11/05 ISSI® IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 1,0 0,1 A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit TSTG Storage Temperature –55 to +150 °C PD Power Dissipation 1.6 W IOUT Output Current (per I/O) 100 mA VIN, VOUT Voltage Relative to Vss for I/O Pins –0.5 to VDDQ + 0.5 V VIN Voltage Relative to Vss for –0.5 to VDD + 0.5 V for Address and Control Inputs VDD Voltage on VDD Supply Relative to Vss –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. |
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