IC41SV4105

2

Integrated Circuit Solution Inc.

DR032-0A 10/29/2001

FEATURES

• Fast Page Mode Access Cycle

• TTL compatible inputs and outputs

• Refresh Interval:

-- 1,024 cycles/16 ms

• Refresh Mode:

RAS-Only,

CAS-before-RAS (CBR), and Hidden

• JEDEC standard pinout

• Single power supply:

1.9V

−

−

−

−

− 2.4V

DESCRIPTION

The

CMOS Dynamic Random Access Memory. The Fast Page

Mode allows 1,024 random accesses within a single row with

access cycle time as short as 20 ns per 4-bit word.

These features make the 4105 Series ideally suited for digital

signal processing, and low power portable audio applications.

The 4105 Series is packaged in a 20-pin 300mil SOJ and a 20

pin TSOP-2

1M x 4 (4

−MBIT) DYNAMIC RAM

WITH FAST PAGE MODE

KEY TIMING PARAMETERS

Parameter

-

50

-70 -100 Unit

50

70

100

ns

20

25

ns

35

50

ns

45

60

ns

90

130

180

ns

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

PIN DESCRIPTIONS

A0-A9

Address Inputs

I/O0-3

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

CAS

Column Address Strobe

Vcc

Power

GND

Ground

PIN CONFIGURATION

20 (26) Pin SOJ, TSOP-2

1

2

3

4

5

9

10

11

12

13

26

25

24

23

22

18

17

16

15

14

I/O0

I/O1

WE

RAS

A9

A0

A1

A2

A3

VCC

GND

I/O3

I/O2

CAS

OE

A8

A7

A6

A5

A4

Preliminary