IC41SV44052

IC41SV44054

2

Integrated Circuit Solution Inc.

DR035-0B 7/31/2002

FEATURES

• Fast Page Mode Access Cycle

• TTL compatible inputs and outputs

• Refresh Interval:

-- 2,048 cycles/32 ms

-- 4,096 cycles/64 ms

• Refresh Mode:

RAS-Only,

CAS-before-RAS (CBR), and Hidden

• JEDEC standard pinout

• Single power supply:

1.9V

−

−

−

−

− 2.7V

DESCRIPTION

The

performance CMOS Dynamic Random Access Memory. The

Fast Page Mode allows 2,048 or 4,096 random accesses within

a single row with access cycle time as short as 20 ns per 4-bit

word.

These features make the 44052/44054 Series ideally suited for

digital signal processing, and low power portable audio

applications.

The 44052/44054 Series is packaged in a 26-pin 300mil SOJ

and a 26 pin TSOP-2

4M x 4 (16-MBIT) DYNAMIC RAM

WITH FAST PAGE MODE

KEY TIMING PARAMETERS

Parameter

-70 -100 Unit

70

100

ns

25

ns

50

ns

60

ns

130

180

ns

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

PIN DESCRIPTIONS

A0-A11

Address Inputs (4K Refresh)

A0-A10

Address Inputs (2K Refresh)

I/O0-3

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

CAS

Column Address Strobe

Vcc

Power

GND

Ground

PIN CONFIGURATION

24 (26) Pin SOJ, TSOP-2

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

VCC

I/O0

I/O1

WE

RAS

*A11(NC)

A10

A0

A1

A2

A3

VCC

GND

I/O3

I/O2

CAS

OE

A9

A8

A7

A6

A5

A4

GND

Preliminary

*A11 is NC for 2K Refresh devices.