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122
P4C1256
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CE
CE
CE
CE CONTROLLED)(6)
Mode
CE
CE
CE
CE
CE
1
CE
2
OE
OE
OE
OE
OE
WE
WE
WE
WE
WE
I/O
Power
Standby
H
X
X
X
High Z
Standby
Standby
X
L
X
X
High Z
Standby
D
OUT
Disabled
L
H
H
H
High Z
Active
Read
L
H
L
H
D
OUT
Active
Write
L
H
X
L
High Z
Active
AC TEST CONDITIONS
TRUTH TABLE
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1256, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the V
CC and ground
planes directly up to the contactor fingers. A 0.01
µF high frequency
capacitor is also required between V
CC and ground.
To avoid signal
OLZ
DOUT
255
Ω
480
Ω
+5V
30pF* (5pF* for t
HZ
, t
LZ
tWZ
OW
and t
,
)
t
OHZ
t
,
,
30pF* (5pF* for t
HZ
, t
LZ
t WZ
OW
and t
,
)
DOUT
166.5
Ω
VTH = 1.73 V
=
R
TH
, t
OHZ,
t OLZ,
reflections, proper termination must be used; for example, a 50
Ω test
environment should be terminated into a 50
Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116
Ω resistor must be used in
series with D
OUT to match 166Ω (Thevenin Resistance).
tDW
WE
ADDRESS
CE
DATA OUT(6)
DATA IN
tWC
DATA VALID
HIGH IMPEDANCE
(9)
tAS
tCW
tAW
tWP
tDH
tAH
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