P4C1256 datasheet(4/8 Pages) ETC1

Part #	P4C1256

Description	HIGH SPEED 32K x 8 STATIC CMOS RAM

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P4C1256

Notes:

1.

WE is HIGH for READ cycle.

2.

CE

1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.

3. ADDRESS must be valid prior to, or coincident with

CE

1 transition

LOW .

4. Transition is measured

± 200 mV from steady state voltage prior to

change, with loading as specified in Figure 1. This parameter is

sampled and not 100% tested.

5. READ Cycle Time is measured from the last valid address to the first

transitioning address.

READ CYCLE NO. 1 (

OE

OE CONTROLLED)(1)

READ CYCLE NO. 2 (ADDRESS CONTROLLED)

READ CYCLE NO. 3 (

CE

CE CONTROLLED)

t

ADDRESS

DATA OUT

AA

t

tOH

DATA VALID

PREVIOUS DATA VALID

(5)

RC

OLZ

ADDRESS

OE

tRC

DATA OUT

(5)

tOH

CE

t

tAC

tOHZ

tHZ

(4)

tOE

tAA

tAC

CE

DATA OUT

tRC

tLZ

(8)

DATA VALID

ICC

ISB

tPU

HIGH IMPEDANCE

tPD

tHZ

VCC SUPPLY

CURRENT

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