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EM78P813BQ Datasheet(PDF) 14 Page - ELAN Microelectronics Corp

Part # EM78P813BQ
Description  8-BIT OTP MICRO-CONTROLLER
Download  65 Pages
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Manufacturer  EMC [ELAN Microelectronics Corp]
Direct Link  http://www.emc.com.tw
Logo EMC - ELAN Microelectronics Corp

EM78P813BQ Datasheet(HTML) 14 Page - ELAN Microelectronics Corp

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EM78P813
8-bit OTP Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
14
2004/8/19
(V1.6)
R1 PAGE1 Interrupt Flag1 real value
7
6
5
4
3
2
1
0
INTR7
INTR6
INTR5
INTR4
INTR3
INTR2
INTR1
INTR0
Bit 0~Bit 7(INTR0~INTR7) : Interrupt flag1 real value. The relation of R1 Page1, RE PAGE0 and IOCE PAGE0 is
shown in fig. When user disable interrupt mask, whether interrupt occur or not , interrupt flag(RE PAGE0) will
appear “0”. Opposite of RE PAGE0, R1 PAGE1 will show real interrupt occur status regardless this interrupt
mask enable or disable. User can clear corresponding external interrupt flag by RE PAGE0 or R1 PAGE1.
Interrupt
Mask
IOCE,IOCF
Interrupt
Flag(RE,RF)
Interrupt
occur
Real Interrupt
Flag(R0 P1,P2)
Fig7 : Relation with interrupt mask ,flag and real flag
R1 PAGE2 Interrupt Flag2 real value
7
6
5
4
3
2
1
0
RBF/STD FSK/CW
X
X
DED
CNT2
CNT1
TCC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0~Bit 3, Bit 6~Bit 7(Internal interrupt flag real value) : Interrupt flag1 real value. The relation of R1 Page2, RF
PAGE0 and IOCF PAGE0 is shown in fig7. When user disable interrupt mask, whether interrupt occur or not ,
interrupt flag(RF PAGE0) will appear “0”. Opposite of RF PAGE0, R1 PAGE1 will show real interrupt occur
status regardless this interrupt mask enable or disable. User can clear corresponding interrupt flag in RF
PAGE0 or R1 PAGE2.
Bit 4~ Bit 5 : Undefined register, these two bits are not allowed to use.
R1 PAGE3 Undefined Register
R1 page3 is undefined register, this is not allowed to use.
R2 Program Counter
External 128K
× 13 PROGRAM ROM addresses to the relative programming instruction codes. The structure is
depicted in Fig.8
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
"RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
"MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to
"0''.
"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared
to "0''.
"TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The
most significant bit (A10~A14) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the
execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
If a interrupt trigger, PROGRAM ROM will jump to address 8 at page0. The CPU will store ACC,R3 status and R5
PAGE automatically, it will restore after instruction RETI.


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