EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

13

2004/8/19

(V1.6)

VII. Function Descriptions

VII.1 Operational Register

05

06

07

08

09

0A

0B

0C

0D

0E

0F

04

03

02

01

R1(TCC Buffer)

R2(PC)

R3(STATUS)

R4(RSR,bank select)

R5(Program page)

R6(Port6 IO data)

R5(Counter setting)

R5(CNT1 low 8 bit data)

R5( CurrentDA control)

R6(DROM data buffer)

R6(CNT1 high 8 bit data)

R6(CurrentDA control)

R7(Port7 IO data)

R8(Port8 IO data)

R9(Port9 IO data)

RB(PortB IO data)

RC(PortC IO data)

RD(PortD IO data)

R7(DROM address)

R8(DROM address)

R7(CNT2 data)

R7(SPI control)

R8(DTMF receiver)

R8(SPI data buffer)

R9(DROM address ,

LCD address MSB )

R9(CMP IO control)

R9(Key tone control)

RA(Power saving , FSK)

RA(LCD address)

RA(Comparator control)

RA(Tont1 control)

RB(LCD data buffer)

RB(Key strobe control)

RB(Tone2 control)

RC(DRAM1 data buffer)

RD(DRAM1 address)

RC(Key strobe control)

RD(LCD control)

RE(Interrupt flag1)

RF(Interrupt flag2)

RE(DRAM1 address ,

DED output)

RE(LCD control ,

Key scan , CAS)

IOC5(Address auto

inc/dec control)

IOC5(DRAM2 data buffer)

IOC6(Port6 I/O control)

IOC6(DRAM2 address)

IOC7(Port7 I/O control)

IOC8(Port8 I/O control)

IOC9(Port9 I/O control)

IOCB(PortB I/O control)

IOCC(PortC I/O control)

IOCD(PortD I/O control)

IOC7(DRAM2 address)

IOC8(IO/SEG switch)

IOC9(PB I/O/SEG switch)

IOCA(PC I/O/SEG switch)

IOCA(STACK point)

IOCB(External LCD driver

control interface)

IOCC(P6 pull high control)

IOCD(P7 pull high control)

IOCE(Interrupt mask1)

IOCE(DED control)

IOCE(Interrupt mask2)

16 Byte Commom register

10

:

1F

Bank0

Bank1

Bank2

Bank3

32x8

32x8

32x8

32x8

Commom register

20

:

3F

R3(6,7)

R3(5)

R4

P1(7,8)

P3(7)

Address

REGISTER

PAGE0

REGISTER

PAGE1

REGISTER

PAGE2

REGISTER

PAGE3

Control

REGISTER

PAGE0

Control

REGISTER

PAGE1

LCD RAM

RA PAGE1 : address

RB PAGE1 : data

DATA ROM

R7 PAGE1 : address(L)

R8 PAGE1 : address(M)

R9 PAGE1 : address(H)

R6 PAGE1 : data

DATA RAM(index1)

RD PAGE1 : address(L)

RE PAGE1 : address(H)

RC PAGE1 : data

DATA RAM(index2)

IOC6 PAGE1 : address(L)

IOC7 PAGE1 : address(H)

IOC5 PAGE1 : data

R4(Unused)

R4(Undefined)

R4(Undefined)

RC(Undefined)

RD(Undefined)

RE(Undefined)

R1(UART receiver buffer)

RF(Undefined)

R1(Real Interrupt flag1)

R1(Real Interrupt flag2)

RF(External Data ROM

Start address LOW)

RF(External Data ROM

Start address HIGH)

Fig.6: control register configuration

VII.2 Operational Register Detail Description

R0 Indirect Addressing Register

R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as

register actually accesses data pointed by the RAM Select Register (R4).

Example:

Mov

A

,

@0x20

;store a address at R4 for indirect addressing

Mov

0x04 ,

A

Mov

A

,

@0xAA ;write data 0xAA to R20 at bank0 through R0

Mov

0x00 ,

A

R1 PAGE0 TCC data buffer

TCC data buffer. Increased by 16.38KHz or by the instruction cycle clock (controlled by CONT register).Written and

read by the program as any other register.