EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

9

2004/8/19

(V1.6)

the digital algorithm detects a recognizable tone-pair (signal

condition). Any momentary loss of signal condition will cause

EST to return to a logic low. This pin shared with PORT61.

STGT

I/O

Steering input/guard time output (bi-directional). A voltage

greater than Vtst detected at ST causes the device to register the

detected tone-pair and update the output latch.

A voltage less than Vtst frees the device to accept a new

tone-pair. The GT output acts to reset the external steering

time-constant; its state is a function of EST and the voltage on

ST . This pin shared with PORT60.

VI. Serial IO, Comparator , Current DA , Tone

Pin

I/O

Description

SCK

I/O

Master: output pin , Slave: input pin.

This pin shared with

PORTD4

SDO

O

Output pin for serial data transferring. This pin shared with

PORTD5.

SDI

I

Input pin for receiving data. This pin shared with PORTD6.

CMP1

I

Comparator input pins. Shared with PORT65.

CMP2

I

Comparator input pins. Shared with PORT66

CMP3

I

Comparator input pins. Shared with PORT67.

DAOUT

O

Current DA output pin. It can be a control signal for sound

generating. Shared with PORTD7.

KTONE

O

Key tone output. Shared with PORT76.

TONE

O

Dual tone output pin

VII. IO

Pin

I/O

Description

P60 ~P67

I/O

PORT 6 can be INPUT or OUTPUT port each bit.

Internal pull high.

P70 ~ P77

I/O

PORT 7 can be INPUT or OUTPUT port each bit.

Internal Pull high function.

Auto key scan function.

Interrupt function.

Shared with Key tone output

P80 ~ P87

I/O

PORT 8 can be INPUT or OUTPUT port each bit.

Shared with LCD Segment signal.

P90 ~ P97

I/O

PORT 9 can be INPUT or OUTPUT port each bit.

Shared with LCD Segment signal.

PB0 ~ PB7

I/O

PORT B can be INPUT or OUTPUT port each bit.

Shared with LCD Segment signal.

PC0 ~ PC7

I/O

PORT C can be INPUT or OUTPUT port each bit.

Shared with LCD Segment signal.

PD0 ~ PD7

I/O

PORT D can be INPUT or OUTPUT port each bit.

Shared with SPI pin

Share with CMP input pin.

P70 ~ P76

I

Interrupt sources. Any pin from PORT70 to PORT76 has a

falling

edge

signal,

it

will

generate

a

corresponding

interruption..

P77

I

Interrupt source. Once PORT77 has a falling edge or rising edge

signal (controlled by CONT register), it will generate a

interruption.

/RESET

I

Low reset