EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

51

2004/8/19

(V1.6)

address R register

page0

R register

page1

R register

page2

R register

page3

IOC register

page0

IOC register

page1

1

--

00000000

00000000

xxxxxxxx

2

--

--

--

--

3

--

--

--

--

4

00xxxxxx

xxxxxxxx

10001000

xxx00000

5

x0000000

00000000

00000000

xxxx0000

11110000

xxxxxxxx

6

xxxxxxxx

xxxxxxxx

00000000

00000000

11111111

xxxxxxxx

7

xxxxxxxx

xxxxxxxx

00000000

00000000

11111111

xxxxxxxx

8

xxxxxxxx

xxxxxxxx

x0000000

xxxxxxxx

11111111

00000000

9

xxxxxxxx

xxxxxxxx

00000xxx

xxxx0000

11111111

00000000

A

00000xx0

xxxxxxxx

00000000

00000000

00000000

00000000

B

xxxxxxxx

xxxxxxxx

11111111

00000000

11111111

00xx0000

C

xxxxxxxx

xxxxxxxx

11111111

00000000

11111111

00000000

D

xxxxxxxx

xxxxxxxx

x0011111

xxxxxxxx

11111111

00000000

E

00000000

xxxxxxxx

10000000

xxxxxxxx

00000000

0x000000

F

00000000

xxxxxxxx

xxxxxxxx

xxxxxxxx

00000000

--

VII.6 wake-up

The controller provided sleep mode for power saving.

SLEEP mode , RA(7)=0 + "SLEP" instruction .

The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or

PLL control (which has enable register), user has to turn it off by software.

Wake-up from SLEEP mode :

(1) WDT time out

(2) external interrupt

(3) /RESET pull low

All these cases will reset controller , and run the program at address zero. The status just like the power on reset.

Be sure to enable circuit at case (1) or (2).

VII.7 Interrupt

RE and RF is the interrupt status register which records the interrupt request in flag bits. IOCE and IOCF is the

interrupt mask register. TCC timer, Counter1 and Counter2 are internal interrupt source. P70 ~ P77(INT0 ~ INT7) are

external interrupt input which interrupt sources are come from the external. If the interrupts are happened by these

interrupt sources, then RE or RF register will generate '1' flag to corresponding register if you enable IOCE or IOCF

register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts

(when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt

service routine the source of the interrupt can be determined by polling the flag bits in the RE and RF register. The

interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to

avoid recursive interrupts.