EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

50

2004/8/19

(V1.6)

VII.4 I/O PORT

M

U

X

0

1

PDRD

PDWR

CLK

C

L

P

R

D

Q

Q

CLK

C

L

P

R

D

Q

Q

PCWR

IOD

PCRD

PORT

Fig.32

The circuit of I/O port and I/O control register

The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the

I/O control registers under program control. The I/O registers and I/O control registers are both readable and writable.

The I/O interface circuit is shown in Fig.27

VII.5 RESET

The RESET can be caused by

(1) Power on voltage detector reset (POVD) and power on reset

(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)

(3) /RESET pin pull low

<Note> At case (1), POVD is controlled by CODE OPTION. If you enable POVD, CPU will reset at 2V under. And

CPU will consume more current about 3uA . And the power on reset is a circuit always enable. It will reset CPU at

about 1.4V and consume about 0.5uA.

Once the RESET occurs, the following functions are performed.

•

The oscillator is running, or will be started.

•

The Program Counter (R2) is set to all "0".

•

When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.

•

The Watchdog timer and prescaler counter are cleared.

•

The Watchdog timer is disabled.

•

The CONT register is set to all "1"

•

The other register (bit7..bit0)