EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

41

2004/8/19

(V1.6)

PAGE3 Undefined register

This register is not allowed to used.

R10~R3F (General Purpose Register)

R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers

VII.3 Special Purpose Registers

A (Accumulator)

Internal data transfer, or instruction operand holding

It's not an addressable register.

CONT ( Control Register )

7

6

5

4

3

2

1

0

INT/EDGE

INT

TS

DAEN

PAB

RSR2

RSR1

RSR0

Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits

PSR2

PSR1

PSR0

TCC rate

WDT rate

0

0

0

1:2

1:1

0

0

1

1:4

1:2

0

1

0

1:8

1:4

0

1

1

1:16

1:8

1

0

0

1:32

1:16

1

0

1

1:64

1:32

1

1

0

1:128

1:64

1

1

1

1:256

1:128

Bit 3(PAB) : Prescaler assignment bit

0/1

TCC/WDT

Bit 4 (DAEN) : Current DA enable control

0/1

disable/enable

Bit 5 (TS) : TCC signal source

0/1

Instruction clock / 16.384K Hz

Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See Fig.15.

Bit 6 (INT) : INT enable flag

0

interrupt masked by DISI or hardware interrupt

1

interrupt enabled by ENI/RETI instructions

Bit 7(INT_EDGE) : interrupt edge type of P77

0

P77 's interruption source is a rising edge signal and falling edge signal.

1

P77 's interruption source is a falling edge signal.

CONT register is readable (CONTR) and writable (CONTW).There is an 8-bit counter available as prescaler for

the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time.

An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register.

See the prescaler ratio in CONT register.Fig.25 depicts the circuit diagram of TCC/WDT. Both TCC and prescaler

will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP

instructions, when assigned to WDT mode.

The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.