EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

40

2004/8/19

(V1.6)

PAGE3 UART transmitter data buffer

7

6

5

4

3

2

1

0

URT7

URT6

URT5

URT4

URT3

URT2

URT1

URT0

Bit 0~Bit 7(URT0~URT7) : Low 8 bit UART transmitter data buffer

RF Interrupt flag

7

6

5

4

3

2

1

0

RBF/SDT FSK/CW

-

UART

DED

CNT2

CNT1

TCC

"1" means interrupt request, "0" means non-interrupt

Bit 0 (TCC) : TCC timer overflow interrupt flag

Set when TCC timer overflows .

Bit 1 (CNT1) : Counter1 timer overflow interrupt flag

Set when counter1 timer overflows.

Bit 2 (CNT2) : Counter2 timer overflow interrupt flag

Set when counter2 timer overflows .

Bit 3 (DED) : Interrupt flag of Differential Energy Detector (DED) output data. If DEDD(RE page2 bit7) has a falling

edge signal (or falling & rising edge signal , switch by IOCE page1 bit5), CPU will set this bit.

Bit 4 (UART) : Universal Asynchronous Receiver Transmitter interrupt flag. When

transmitter buffer empty , receiver buffer full or receiver data error, this bit will be set.

Bit 5Undefined register. Note that this bit is not ensured to be a fix value.

Bit 6 (FSK/CW) : FSK data or Call waiting data interrupt flag.

If FSKDATA or CAS has a falling edge trigger signal, CPU will set this bit.

Bit 7 ( RBF/STD) : SPI data transfer complete or DTMF receiver signal valid interrupt

If serial IO 's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set

this bit. Or DTMF receiver's STD signal has a rising edge signal (DTMF decode a DTMF signal).

IOCF is the interrupt mask register. User can read and clear.

Trigger edge as the table

Signal

Trigger

<Note>

TCC

Time out

COUNTER1

Time out

8/16 bits select by CONT register

COUNTER2

Time out

DED

Signal detect

UART

Receiver full, Transmitter

empty or error(if enable)

ADI

AD sampling success

FSK

Falling edge

RBF/STD

Rising edge

EM78813 MCU will store ACC,R3 status and R5 PAGE automatically after an interrupt is triggered.

And it will be restored after instruction “RETI”.

PAGE2 External Data ROM

7

6

5

4

3

2

1

0

EXA8

EXA7

EXA6

EXA5

EXA4

EXA3

EXA2

EXA1

Bit 0~Bit 7(EXA1~EXA8) : Expanding Data ROM start address A1~A8

PAGE2 External Data ROM

7

6

5

4

3

2

1

0

EXA16

EXA15

EXA14

EXA13

EXA12

EXA11

EXA10

EXA9

Bit 0~Bit 7(EXA9~EXA16) : Expanding Data ROM start address A9~A16