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EM78P813BQ Datasheet(PDF) 36 Page - ELAN Microelectronics Corp |
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EM78P813BQ Datasheet(HTML) 36 Page - ELAN Microelectronics Corp |
36 / 65 page EM78P813 8-bit OTP Micro-controller __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 36 2004/8/19 (V1.6) PAGE3 Undefined register This register is not allowed to used. RE Interrupt flag1 , Data RAM address1(H) CAS , LCD Control , Key Scan , PAGE0 Interrupt flag1 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Bit 0 (INT0) : External INT0 pin interrupt flag If PORT70 has a falling edge trigger signal. CPU will set this bit. Bit 1 (INT1) : External INT1 pin interrupt flag If PORT71 has a falling edge trigger signal. CPU will set this bit. Bit 2 (INT2) : External INT2 pin interrupt flag If PORT72 has a falling edge trigger signal. CPU will set this bit. Bit 3 (INT3) : External INT3 pin interrupt flag If PORT73 has a falling edge trigger signal. CPU will set this bit. Bit 4 (INT4) : External INT4 pin interrupt flag If PORT74 has a falling edge trigger signal. CPU will set this bit. Bit 5 (INT5) : External INT5 pin interrupt flag If PORT75 has a falling edge trigger signal. CPU will set this bit. Bit 6 (INT6) : External INT6 pin interrupt flag If PORT76 has a falling edge trigger signal. CPU will set this bit. Bit 7 (INT7) : External INT7 pin interrupt flag If PORT77 has a falling (or rising and falling) edge trigger signal. CPU will set this bit. Signal Trigger <Note> INT0 : INT6 Falling edge INT7 Falling/Falling & rising edge Controlled by CONT register PAGE1 Data RAM Address1(H) 7 6 5 4 3 2 1 0 RAM1A13 RAM1A12 RAM1A11 RAM1A10 RAM1A9 RAM1A8 Bit 0~Bit 5(RAM1A8 ~ RAM1A13) : Data RAM address (address8 to address13) for RAM reading. Bit 6~Bit 7 : Unused PAGE2 CAS , LCD Control , Key Scan 7 6 5 4 3 2 1 0 CAS KEYSTROB KEYSCAN LCD1 LCD0 LCDM1 LCDM0 Bit 0~Bit 1(LCDM0~LCDM1) : LCD common mode, bias select and COM/SEG switch control bits LCDM1 LCDM0 COM output mode LCD bias COM/SEG switch 0 0 32 common 1/7 COM 16 ~ COM 31 select 0 1 24 common 1/6 COM 16 ~ COM 23 , SEG98 ~ SEG 105 select 1 X 16 common 1/5 SEG 98 ~ SEG 111 select <Note> When 32 LCD common mode is set, COM16/SEG111 pin ~ COM31/SEG98 pin are set to COM16 ~ COM31 and LCD bias is switch 1/7 bias. When 24 LCD common mode is set, COM16 pin ~ COM23/SEG106 pin are set to COM16 ~ COM23 and COM24/SEG105 pin ~ COM31/SEG98 pin are set to SEG105 ~ SEG98. When 16 LCD common mode is set, COM16 pin ~ COM31/SEG98 pin are set to SEG1131~ SEG98. |
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