EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

27

2004/8/19

(V1.6)

no data is present, the bit 2 (DATA) of register RA is held on “1” state. This is accomplished by an carrier detect circuit

which determines if the in-band energy is high enough. If the incoming signal is valid, bit 1 (/CD) of register RA will be

“0” otherwise it will be held on “1”. And thus the demodulated data is transferred to bit 2 (DATA) of register RA. If it is

not, then the FSK demodulator is blocked.

Bit 3 (ROMRI) : External Data ROM read data address auto_increase enable.

RO_IDEN

ROMRI

Result

0

X

Regardless Read/Write external Data ROM,

Address flag cannot increase or decrease.

1

0

Address flag will auto_increase or decrease

after Read/Write external Data ROM

1

1

Address flag will auto_increase or decrease

after Write external Data ROM, but address

flag is constant after read external Data ROM.

Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits

User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.

PLLEN

CLK1

CLK0

Sub clock

MAIN clock

CPU clock

1

0

0

32.768kHz

5.374MHz

5.374MHz (Normal mode)

1

0

1

32.768kHz

1.7913MHz

1.7913MHz (Normal mode)

1

1

0

32.768kHz

10.7479MHz

10.7479MHz (Normal mode)

1

1

1

32.768kHz

3.5826MHz

3.5826MHz (Normal mode)

0

Don’t care

don’t care

32.768kHz

Don’t care

32.768kHz (Green mode)

0

Don’t care

don’t care

32.768kHz

Don’t care

32.768kHz (Green mode)

0

Don’t care

don’t care

32.768kHz

Don’t care

32.768kHz (Green mode)

0

Don’t care

don’t care

32.768kHz

Don’t care

32.768kHz (Green mode)

Bit 6 (PLLEN) : PLL enable control bit

It is CPU mode control register. If PLL is enabled, CPU will operate at normal mode (high frequency , main

clock); otherwise, it will run at green mode (low frequency, 32768 Hz).

0/1

disable/enable

Sub-clock

32.768kHz

PLL

switch

0

ENPLL

CLK1 ~ CLK0

1

System clock

3.5826M Hz to analog circuit

=>5.374M Hz

=>1.7913M Hz

=>3.5826M Hz

=>10.7479M Hz

1.5

2

3

×

1

×

÷

×

Fig.19

The relation between 32.768kHz and PLL