EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

26

2004/8/19

(V1.6)

Bit 1 (/CD) : FSK carrier detect indication

0/1

Carrier Valid/Carrier Invalid

It's a read only signal. If FSK decoder detect the energy of mark or space signal. The Carrier signal will go to

low level. Otherwise it will go to high.. Note!! Should be at normal mode.

Bit 2 (FSKDATA) : FSK decoding data output

It's a read only signal. If FSK decode the mark or space signal , it will output high level signal or low level

signal at this register. It's a raw data type. That means the decoder just decode the signal and has no process on

FSK signal. Note!! Should be at normal mode.

User can use FSK data falling edge interrupt function to help data decoding.

Example:

MOV

A,@01000000

IOW

IOCF

;enable FSK interrupt function

CLR

RF

ENI

;wait for FSK data's falling edge

:

0 = Space data ( 2200Hz )

1 = Mark data (1200Hz)

FSK block power is controlled by R5 page3 bit3,4. When PCTRI1=0 and PCTRL0=1 , FSK power on.

The relation between R5 bit3 to bit4 and RA bit1 to bit 2 are show in Fig.14. You have to power FSK decoder

up first, then wait a setup time (Tsup) and check carrier signal (/CD). If the carrier is low, program can process the

FSK data.

TIP/RING

/CD

FSKDATA

FIRST RING

2 SECONDS

0.5 SEC

0.5 SEC

SECOND RING

2 SECONDS

DATA

Tcdl

PCTRL0

Tdoc

Tcdh

Tsup

FSK signal

PCTRL1

Fig.18

The relation between R5 bit3 to bit4 and RA bit1 to bit 2

The controller is a CMOS device designed to support the Caller Number Deliver feature which is offered by the

Regional Bell Operating Companies. The FSK block comprises one path: the signal path. The signal path consist of an

input differential buffer, a band pass filter, an FSK demodulator and a data valid with carrier detect circuit.

In a typical application, user can use his own external ring detect output as a triggering input to IO port. User

can use this signal to wake up whole chip by external ring detect signal. By setting “0,1” to R5 b4 and b3 (PCTRL1 &

PCTRL0) of register RA to activate the block of FSK decoder. If b4 and b3 of register R5 is set to “0,1”, the block of

FSK decoder will be powered down.

The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this signal

to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends it to a post filter.

The output data is then made available at bit 2 (FSKDATA) of register RA. This data, as sent by the central office, includes

the header information (alternate "1" and "0") and 150 ms of marking which precedes the date, time and calling number. If