EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

25

2004/8/19

(V1.6)

PAGE2 OP input control Register, FSK/CW/DTMF Power select

7

6

5

4

3

2

1

0

PCTRL1 PCTRL0

ADCS3

ADCS2

ADCS1

-

-

-

Bit 0 ~ Bit 2 : Unused.

Bit 3 ~ Bit 5(ADCS1 ~ ADCS3) : PORT65 ~ PORT67 normal IO or CMP input control bit.

ADCSX = 1

Comparator input

ADCSX = 0

normal IO

Bit 6~Bit 7 (PCTRL0~PCTRL1) : FSK,CW and DTMF receiver power control bits

PCTRL1

PCTRL0

Select

Relation Register

0

0

FSK and DTMFr power off

-

0

1

FSK power on

RA PAGE0

1

0

DTMF receiver power on

R8 PAGE2

1

1

Can not used

*Please do not set 1 to both the bits, or FSK and DTMFr function will fail..

*When User turn on DTMF receiver power, PORT60 and PORT61 will switch to /STGT and

EST pin.

PAGE3 KEY Tone Control

7

6

5

4

3

2

1

0

URT8

URR8

DA1

DA0

URINV

KT1

KT0

KTS

Bit 0 (KTS) : Key tone output switch

0

normal PORT76

1

key tone output .

Bit 1 ~ Bit 2 (KT0 ~ KT1) : Key tone output frequency and its power control

KT1

KT0

Key tone frequency and power

0

0

32.768KHz/32 = 1.024kHz clock and enable

0

1

32.768KHz/16 = 2.048kHz clock and enable

1

0

32.768KHz/8 = 4.096kHz clock and enable

1

1

Power off key tone

Bit 3(URINV) : Enable UART TXD, RXD port inverse output

0

Disable UART TXD, RXD port inverse output

1

Enable UART TXD, RXD port inverse output

Bit 4 ~ Bit 5(DA0~DA1) :These two bits are the least significant 2 bits of Current DA. Combine R6 PAGE3 and

these 2 bits as complete 10 bits Current DA output data.

Bit 6(URR8) : MSB of UART receiver data buffer.

Bit 7(URT8) : MSB of UART transmitter data buffer.

RA CPU Power saving , main CLK select , FSK , WDT timer , LCD address

Comparator control , Tone1 generator

PAGE0 Power saving , main CLK select , FSK , WDT timer

7

6

5

4

3

2

1

0

0

PLLEN

CLK1

CLK0

ROMRI FSKDATA

/CD

WDTEN

Bit 0 (WDTEN) : Watch dog control register

User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If the

prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler assigns to

WDT, the time of time out will be more times depending on the ratio of prescaler.

0/1

disable/enable