EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

24

2004/8/19

(V1.6)

TONE

TONE

EST

ST/GT

Vtst

1/2 VDD

Q4..Q1

STD

LINE_ENG

Tdp

5~20mS

by S/W

Tgta

30mS Typ.

Tgtp

30mS Typ.

Tpq

8 uS Typ.

Fig.17

DTMF receiver timing.

Bit 7 (CMPFLAG) : Comparator output flag

0

Input voltage < reference voltage

1

Input voltage > reference voltage

<Note>Please refer to RA page 2 comparator control register .

PAGE3 SPI Data buffer

7

6

5

4

3

2

1

0

SPIB7

SPIB6

SPIB5

SPIB4

SPIB3

SPIB2

SPIB1

SPIB0

Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer

If you write data to this register, the data will write to SPIW register. If you read this data, it will read the data

from SPIR register. Please refer to Fig.9

R9 Port 9 I/O Data , LCD address MSB , Data ROM address ,OP , Key tone control,

PAGE0 Port 9 I/O Data

7

6

5

4

3

2

1

0

P97

P96

P95

P94

P93

P92

P91

P90

Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9 ( 0~7 ) I/O data register

User can use IOC register to define input or output each bit.

PAGE1 LCD address MSB , Data ROM address

7

6

5

4

3

2

1

0

LCDA8

DRA20

DRA19

DRA18

DRA17

DRA16

Bit 0 ~ Bit 4 (DRA16 ~ DRA20) : Data ROM address(16~20) for ROM reading..

Bit 5~Bit 6 : Unused

Bit 7 (LCDA8) : MSB of LCD address for internal LCD RAM reading or writing

Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0.

For LCD address access over 0xFFH, set this bit to “1”; otherwise set this bit to “0”.