EM78P813

8-bit OTP Micro-controller

__________________________________________________________________________________________________________________________________________________________________

* This specification is subject to change without notice.

22

2004/8/19

(V1.6)

SDO

RBF

SCK

(SCES=0)

SCK

(SCES=1)

SDI

Shift data out

Shift data in

Clear by software

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Fig.15

SPI timing

R8 Port 8 I/O Data , Data ROM address , DTMF receiver , SPI Data

PAGE0 Port 8 I/O Data

7

6

5

4

3

2

1

0

P87

P86

P85

P84

P83

P82

P81

P80

Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8 ( 0~7 ) I/O data register

User can use IOC register to define input or output each bit.

PAGE1 Data ROM address

7

6

5

4

3

2

1

0

DRA15

DRA14

DRA13

DRA12

DRA11

DRA10

DRA9

DRA8

Bit 0 ~ Bit 7 (DRA8 ~ DRA15) : Data ROM address ( 8~15 ) for ROM reading

PAGE2 DTMF Receive

7

6

5

4

3

2

1

0

CMPFLAG

STD

-

-

Q4

Q3

Q2

Q1

Bit 0 ~ Bit 3 (Q1 ~ Q4) : DTMF receiver decoding data

To provide the code corresponding to the last valid tone-pair received (see code table). STD signal which

steering output presents a logic high when a received tone-pair has been registered and the Q4 ~ Q1 output latch

updated and generate a interruption (IOCF has enabled); returns to logic low when the voltage on ST/GT falls

below Vtst.

F low

F high

Key

DREN

Q4~Q1

697

1209

1

1

0001

697

1336

2

1

0010

697

1477

3

1

0011