EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

20

2004/8/19

(V1.6)

Bit 0

SPI module

SCK

Bit7

Salve Device

SPIR register

SDI

SPIW register

SPIS Reg

SDO

SDO

SCK

SDI

Master Device

R5 page1

Fig.13

Single SPI Master / Salve Communication

Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits

SBR2

SBR1

SBR0

Mode

Baud rate

0

0

0

Master

Fsco

0

0

1

Master

Fsco/2

0

1

0

Master

Fsco/4

0

1

1

Master

Fsco/8

1

0

0

Master

Fsco/16

1

0

1

Master

Fsco/32

1

1

0

Slave

1

1

1

X

<Note> Fsco = CPU instruction clock

For example :

If PLL enable and RA PAGE0 (Bit5,Bit4)=(1,1), instruction clock is 3.58MHz/2

Fsco=3.5862MHz/2

If PLL enable and RA PAGE0 (Bit5,Bit4)=(0,0), instruction clock is 0.895MHz/2

Fsco=0.895MHz/2

If PLL disable, instruction clock is 32.768kHz/2

Fsco=32.768kHz/2.

Bit 3 (SCES) : SPI clock edge selection bit

1

Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.

0

Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.

Bit 4 (SE) : SPI shift enable bit

1

Start to shift, and keep on 1 while the current byte is still being transmitted.

0

Reset as soon as the shifting is complete, and the next byte is ready to shift.

<Note> This bit has to be reset in software.

Bit 5 (SRO) : SPI read overflow bit

1

A new data is received while the previous data is still being hold in the SPIB register. In this situation, the

data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB register even

if the transmission is implemented only.

0

No overflow

<Note> This can only occur in slave mode.

Bit 6 (SPIE) : SPI enable bit

1

Enable SPI mode

0

Disable SPI mode

Bit 7 (RBF) : SPI read buffer full flag

1

Receive is finished, SPIB is full.

0

Receive is not finish yet, SPIB is empty.