HN58X2508I/HN58X2516I

Rev.2.00, Aug.19.2004, page 24 of 27

Hold Condition

The hold (

HOLD) signal is used to pause any serial communications with the device without resetting the

clocking sequence.

During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial

clock (C) are don’t care.

To enter the hold condition, the device must be selected, with chip select (

S) low.

Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device

while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be

used if it is required to reset any processes that had been in progress.

The hold condition starts when the hold (

HOLD) signal is driven low at the same time as serial clock (C)

already being low (as shown in the following figure).

The hold condition ends when the hold (

HOLD) signal is driven high at the same time as serial clock (C)

already being low.

The following figure also shows what happens if the rising and falling edges are not timed to coincide with

serial clock (C) being low.

Hold Condition Activation

C

HOLD

HOLD status

HOLD status