HN58X2508I/HN58X2516I

Rev.2.00, Aug.19.2004, page 22 of 27

Data Protect

The protection features of the device are summarized in the following table. When the Status Register Write

Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status

Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction, regardless weather write protect (

W) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be

considered, depending on the state of write protect (

W):



If write protect (

W) is driven high, it is possible to write to the Status Register provided that the

Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.



If write protect (

W) is driven low, it is not possible to write to the Status Register even if the

Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.

(Attempts to write to the Status Register are rejected, and are not accepted for execution). As a

consequence, all the data bytes in the memory area that are software protected (SPM) by the Block

Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:



By setting the Status Register Write Disable (SRWD) bit after driving write protect (

W) low.



By driving write protect (

W) low after setting the Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (

W) high.

If write protect (

W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated,

and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register,

can be used.

Write Protected Block Size

Status register bits

Array addresses protected

BP1

BP0

Protected blocks

HN58X2516I

HN58X2508I

0

0

None

None

None

0

1

Upper quarter

600h

− 7FFh

300h

− 3FFh

1

0

Upper half

400h

− 7FFh

200h

− 3FFh

1

1

Whole memory

000h

− 7FFh

000h

− 3FFh