HN58X2508I/HN58X2516I

Rev.2.00, Aug.19.2004, page 20 of 27

Write to Memory Array (WRITE):

As shown in the following figure, to send this instruction to the device, chip select (

S) is first driven low.

The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input

(D).

The instruction is terminated by driving chip select (

S) high at a byte boundary of the input data. In the case

of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the

instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period

If, though, chip select (

S) continues to be driven low, as shown in the following figure, the next byte of the

input data is shifted in, so that more than a single byte, starting from the given address towards the end of the

same page, can be written in a single internal Write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address counter are

incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address

counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming

data. (The page size of these device is 32 bytes).

The instruction is not accepted, and is not executed, under the following conditions:



If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)



If a Write cycle is already in progress



If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.

Byte Write (WRITE) Sequence (1 Byte)

S

W

C

D

Q

16-Bit Address

Data Byte 1

01

2

3

4

5

6

7

0

1

2

3

13

14

15

8

9

10

20

21 22 23 24 25 26 27 28 29 30

31

High-Z

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

4

5

6

7

0

1

2

3

Instruction

Note:

1. Depending on the memory size, as shown in Address Range Bits table, the most significant address

bits are don’t care.