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MAX9401EHJ Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX9401EHJ Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 13 page ![]() cables. External termination is required. See the Output Termination section. Enable Setting EN = high and EN = low enables the outputs. Setting EN = low and EN = high forces the outputs to a differential low when disabled. All changes on CLK, SEL, and IN_ are ignored. Asynchronous Operation Setting SEL = high and SEL = low enables four chan- nels to operate independently as a buffer/receiver (CLK is ignored). In asynchronous mode, the CLK sig- nal should be set to either logic low or high state to min- imize noise coupling. Synchronous Operation Setting SEL = low and SEL = high enables all four channels to operate in synchronous mode. In this mode, buffered inputs are clocked into flip-flops simul- taneously on every rising edge of the differential clock input (CLK and CLK). Differential Signal Input Limit The maximum differential input signal magnitude is 3.0V. Supply Voltages For interfacing to differential PECL signals, the VCC range is from +3.0V to +5.5V (with VEE grounded). For interfacing to differential ECL, the VEE range is -3.0V to -5.5V (with VCC grounded). Output levels are refer- enced to VCC and are considered PECL or ECL, depending on the level of the VCC supply. Applications Information Input Bias Unused inputs should be biased to avoid noise cou- pling that might cause toggling at the unused outputs. See Figure 2 for the biasing network. Output Termination Terminate the outputs through 50 Ω to VCC - 3.3V or use an equivalent Thevenin termination. Use identical termi- nations on each OUT for the lowest skew. When a sin- gle-ended signal is taken from a differential output, terminate both outputs. For example, if OUT_ is used as a single-ended output, terminate both OUT_ and OUT_. Quad ECL/PECL Differential Buffers/Receivers 6 _______________________________________________________________________________________ Figure 1. MAX9401/MAX9404 Input and Output Configurations IN_ IN_ IN_ 100 Ω IN_ VCC OUT_ OUT_ MAX9401 MAX9401 MAX9404 MAX9404 Figure 2. Input Bias Circuits for Unused Pins for MAX9401/MAX9404 IN_ IN_ 100 Ω 1k Ω VCC VEE IN_ IN_ 1k Ω VCC VEE MAX9401 MAX9404 100 Ω |
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