Quad ECL/PECL Differential

Buffers/Receivers

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3

Note 1: Measurements are made with the device in thermal equilibrium.

operating range.

Note 4: Outputs are open. Inputs driven high or low.

Note 5: Guaranteed by design and characterization. Limits are set to ±6 sigma.

Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition.

Note 7: Device jitter added to the input signal.

AC ELECTRICAL CHARACTERISTICS

(Notes 1, 5)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

IN to OUT Differential

Propagation Delay

SEL = high, Figure 4

300

365

550

ps

CLK to OUT Differential

Propagation Delay

SEL = low, Figure 5

580

620

758

ps

IN to OUT Channel-to-Channel

Skew

SEL = high (Note 6)

15

55

ps

CLK to OUT Channel-to-

Channel Skew

SEL = low (Note 6)

10

40

ps

Maximum Clock Frequency

≥ 900mV, SEL = low

3.0

GHz

Maximum Data Frequency

≥ 900mV

1.5

GHz

clock

1.4

2.5

Added Random Jitter (Note 7)

0.9

2.7

ps

(RMS)

2

20

30

Added Deterministic Jitter

(Note 7)

SEL = high, IN_ = 1.5Gbps, 2

pattern

36

55

IN to CLK Setup Time

Figure 5

80

ps

CLK to IN Hold Time

Figure 5

80

ps

Output Rise Time

Figure 4

116

145

ps

Output Fall Time

Figure 4

115

145

ps

Propagation Delay Temperature

Coefficient

1

ps/

°C