taining the distance between differential traces and

avoid sharp corners. Minimize the number of vias to

prevent impedance discontinuities. Reduce reflections

by maintaining the 50

Ω characteristic impedance

through connectors and across cables. Minimize skew

by matching the electrical length of the traces.

Chip Information

TRANSISTOR COUNT: 748

PROCESS: Bipolar

Quad ECL/PECL Differential

Buffers/Receivers

8

_______________________________________________________________________________________

Figure 5. CLK to OUT Propagation Delay Timing Diagram

CLK

CLK

IN_

IN_

OUT_

OUT_

(SEL = LOW, EN = HIGH)