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OLED-016O002C-SPP3N00000 Datasheet(PDF) 8 Page - Vishay Siliconix |
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OLED-016O002C-SPP3N00000 Datasheet(HTML) 8 Page - Vishay Siliconix |
8 / 26 page ![]() OLED-016O002C-SPP3N00000 www.vishay.com Vishay Revision: 18-Aug-16 8 Document Number: 37796 For technical questions, contact: displays@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 4. Interface Pin Function Pin No. Symbol Pin Type Description 1NC No connection 2VSL P This is segment voltage (output low level) reference pin. When external VSL is not used, this pin should be left open. When external VSL is used, connect with resistor and diode to ground (details depend on application). 3 VSS P Ground pin. It must be connected to external ground. 4 REGVDD I Internal VDD regulator selection pin in 5V I/O application mode. When this pin is pulled HIGH, internal VDD regulator is enabled (5V I/O application). When this pin is pulled LOW, internal VDD regulator is disabled (Low voltage I/O application). 5SHLC I This pin is used to determine the Common output scanning direction. COM scan direction SHLC COM scan direction 1 COM0 to COM31 (Normal) 0 COM31 to COM0 (Reverse) Note (1) 0 is connected to VSS (2) 1 is connected to VDDIO 6SHLS I This pin is used to change the mapping between the display data column address and the Segment driver. SEG scan direction SHLS SEG direction 1 SEG0 to SEG99 (Normal) 0 SEG99 to SEG0 (Reverse) Note (1) 0 is connected to VSS (2) 1 is connected to VDDIO 7 VDD P Power supply for core logic operation. VDD can be supplied externally or regulated internally. In LV IO application (internal VDD is disabled), this is a power input pin. In 5V IO application (internal VDD is enabled), VDD is regulated internally from VDDIO. A capacitor should be connected between VDD and VSS under all circumstances. 8 VDDIO P Low voltage power supply and power supply for interface logic level in both Low Voltage I/O and 5V I/O application. It should match with the MCU interface voltage level and must be connected to external source. 9BS0 I MCU bus interface selection pins. Select appropriate logic setting as described in the following table. BS2, BS1 and BS0 are pin select. Bus Interface selection 10 BS1 |
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