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STA8089FG Datasheet(PDF) 27 Page - STMicroelectronics |
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STA8089FG Datasheet(HTML) 27 Page - STMicroelectronics |
27 / 34 page ![]() DocID027175 Rev 8 27/34 STA8089FG Electrical characteristics 33 Figure 4. 32.768 kHz crystal connection To drive the 32.768 kHz crystal pins from an external clock source: Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This disables the internal inverter, thus reducing the power consumption to minimum. Drive the RTC_XTI pin with a square signal or a sine wave. 4.8.3 OSCI oscillator specifications The supported values of the embedded BOOT ROM are 16.368 MHz, 24.00 MHz, 26.00 MHz and 48.00 MHz. The default values supported by the GNSS binary image is 26MHz and 48MHz, to enable USB peripheral the 48 MHz is mandatory. 4.8.4 ADC specifications This section gives the AC specification of the 10 bit Successive Approximation Register ADC embedded in STA8089FG device. It is controlled by the ARM9 MCU through a wrapper and an APB bridge as depicted in Figure 5 and it has a maximum conversion rate of 1MSPS with 8 muxed analog input channels capability. An internal voltage reference is used and analog/digital power supplies connections are implemented inside the device without any needs of dedicated external pins. Table 23. Characteristics of external slow clock input Symbol Parameter Min. Typ. Max. Unit TJIT (cc) Cycle-to-cycle jitter -70 — 70 ps TJIT (per) Period jitter -70 — 70 ps Variation -500 — 500 ppm TDUTY Duty cycle 45 — 55 % CL = 18 pF CL = 18 pF 32.768 kHz Crystal RTC_XTII RCT_XTO Device |
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