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SI8440 Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI8440 Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 24 page Si8440/1/2 Rev. 0.3 5 Timing Characteristics Maximum Data Rate 0 — 100 Mbps Minimum Pulse Width — 5 — ns Propagation Delay1 tPHL, tPLH —7.5 — ns Pulse Width Distortion |tPLH - tPHL|1 PWD — 1 — ns Propagation Delay Skew2 tPSK —6 — ns Channel-Channel Skew3 tPSKCD/OD —0.5 — ns Output Rise Time C1 = 15 pF — 2 — ns Output Fall Time C1 = 15 pF — 2 — ns Common Mode Transient Immunity at Logic Low Output4 CML 25 30 — kV/µs Common Mode Transient Immunity at Logic High Output4 CMH 25 30 — kV/µs Enable to Data Valid ten1 —5 — ns Enable to Data Tri-State ten2 —5 — ns Start-up Time5 tSU —3 — µs Notes: 1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 4. CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 5. Start-up time is the time period from the application of power to valid data at the output. Table 1. Electrical Characteristics (Continued) (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 C°) Parameter Symbol Test Condition Min Typ Max Unit Figure 1. ENABLE Timing Diagram Figure 2. Propagation Delay Timing ENABLE OUTPUTS ten1 ten2 INPUT (VIX) OUTPUT (VOX) tPLH tPHL 50% 50% |
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