Si550

4

Preliminary Rev. 0.3

Symmetry (duty cycle)

SYM

LVPECL:

LVDS:

1.25 V (diff)

CMOS:

45

—

55

%

Notes:

1. 50

Table 5. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

φ

J

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.35

0.38

—

—

ps

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.43

0.41

—

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.52

0.46

—

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.64

0.52

—

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.42

0.58

—

—

ps

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.48

0.60

—

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.57

0.64

—

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.67

0.68

—

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

Table 4. CLK± Output Levels and Symmetry (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units