AM2432...ALV datasheet(234/280 Pages) TI

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7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch

For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -

Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.

7.10.5.16.6.1 PRU_ICSSG MDIO Timing

Table 7-127, Table 7-128, Table 7-129, and Figure 7-106 present timing conditions, requirements, and switching

characteristics for PRU_ICSSG MDIO.

Table 7-127. PRU_ICSSG MDIO Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

470

Table 7-128. PRU_ICSSG MDIO Timing Requirements

see Figure 7-106

NO.

PARAMETER

MIN

MAX

UNIT

MDIO1 tsu(MDIO_MDC)

Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high

MDIO2 th(MDC_MDIO)

Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high

Table 7-129. PRU_ICSSG MDIO Switching Characteristics

see Figure 7-106

NO.

PARAMETER

MIN

MAX

UNIT

MDIO3 tc(MDC)

Cycle time, MDIO[x]_MDC

400

MDIO4 tw(MDCH)

Pulse Duration, MDIO[x]_MDC high

160

MDIO5 tw(MDCL)

Pulse Duration, MDIO[x]_MDC low

160

MDIO7 td(MDC_MDIO)

Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid

-150

150

MDIO3

MDIO1

MDIO2

MDIO7

MDIO4

MDIO5

MDIO[x]_MDC

MDIO[x]_MDIO

(input)

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

Figure 7-106. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics

AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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