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AM2432...ALV Datasheet(PDF) 227 Page - Texas Instruments |
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AM2432...ALV Datasheet(HTML) 227 Page - Texas Instruments |
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227 / 280 page ![]() 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Table 7-111. PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 3 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 18 pF 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Table 7-112. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode see Figure 7-95 and Figure 7-96 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSD1 tc(SD_CLK) Cycle time, SDx_CLK 40 ns PRSD2L tw(SD_CLKL) Pulse duration, SDx_CLK low 20 ns PRSD2H tw(SD_CLKH) Pulse duration, SDx_CLK high 20 ns PRSD3 tsu(SD_D-SD_CLK) Setup time, SDx_D valid before SDx_CLK active edge 10 ns PRSD4 th(SD_CLK-SD_D) Hold time, SDx_D valid before SDx_CLK active edge 5 ns SDx_CLK PRU_TIMING_07 PRSD2H PRSD2L PRSD4 PRSD3 SDx_D PRSD1 Figure 7-95. PRU_ICSSG PRU SD_CLK Falling Active Edge SDx_CLK PRSD2L PRSD3 PRSD4 PRU_TIMING_08 SDx_D Figure 7-96. PRU_ICSSG PRU SD_CLK Rising Active Edge www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 227 Product Folder Links: AM2434 AM2432 AM2431 |
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