AM2432...ALV datasheet(135/280 Pages) TI

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7.10.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,

see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Table 7-4. System Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

7.10.3.1 Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset

related signals.

Table 7-5. MCU_PORz Timing Requirements

see Figure 7-7

NO.

PARAMETER

MIN

MAX UNIT

RST1

th(SUPPLIES_VALID - MCU_PORz)

Hold time, MCU_PORz active (low) at Power-up

after supplies valid (using external crystal)

9500000

RST2

Hold time, MCU_PORz active (low) at Power-up

after supplies valid and external clock stable (using

external LVCMOS oscillator)

1200

RST3

tw(MCU_PORzL)

Pulse Width minimum, MCU_PORz low after

Power-up (without removal of Power or system

reference clock MCU_OSC0_XI/XO)

1200

Figure 7-7. MCU_PORz Timing Requirements

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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