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GS9092 Datasheet(PDF) 1 Page - Gennum Corporation |
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GS9092 Datasheet(HTML) 1 Page - Gennum Corporation |
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1 / 58 page  www.gennum.com GS9092 GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI GS9092 Data Sheet 28202 - 2 September 2005 1 of 58 Key Features • SMPTE 259M-C compliant scrambling and NRZI to NRZ encoding (with bypass) • DVB-ASI sync word insertion and 8b/10b encoding • Integrated Cable Driver • Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet insertion, and ancillary data packet insertion • User selectable additional processing features including: • ANC data checksum, and line number calculation and insertion • TRS and EDH packet generation and insertion • illegal code remapping • Enhanced Gennum Serial Peripheral Interface (GSPI) • JTAG test interface • +1.8V internal cable driver and core power supply • Optional +1.8V or +3.3V digital I/O power supply • Small footprint (8mm x 8mm) • Low power operation (typically 170mW) • Pb-free and RoHS compliant Applications • SMPTE 259M-C Serial Digital Interfaces • DVB-ASI Serial Digital Interfaces Description The GS9092 is a 270Mb/s serializer with an internal FIFO and an integrated cable driver. It contains all the necessary blocks to realize a transmit solution for SD-SDI and DVB-ASI applications. In addition to serializing the input data stream, the GS9092 performs NRZI-to-NRZ encoding and scrambling as per SMPTE 259M-C when operating in SMPTE mode. When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization. Parallel data inputs are provided for 10-bit multiplexed formats at SD signal rates. A 27MHz parallel clock input signal is also required. The integrated cable driver features an adjustable signal swing and common mode operating point offering fully compliant SMPTE 259M-C cable driver connectivity. The GS9092 includes a range of data processing functions such as automatic standards detection and EDH support. The device can also insert TRS signals, re-map illegal code words, and generate and insert SMPTE 352M payload identifier packets. All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. The GS9092 also incorporates a video line-based FIFO. This FIFO may be used in four user-selectable modes to carry out tasks such as data delay, clock phase interchange, MPEG packet insertion and clock rate interchange, and ancillary data packet insertion. The device may also be used as a low-latency parallel-to-serial converter where the SMPTE scrambling block will be the only processing feature enabled. The GS9092 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS compliant). |
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