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TLE9185QXV33 Datasheet(PDF) 18 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 18 Page - Infineon Technologies AG |
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18 / 192 page  TLE9185QXV33 BLDC Driver System Features Datasheet 18 Rev.1.0 2021-01-21 Note: If during monitoring the INTN/TEST pin for Software Development Mode entry, the device changes the mode without SPI command, the device will not enter/stay in Software Development Mode. CRC configuration detail The CRC is configured using the following scheme: • Pull-down on PWM1/CRC enable the CRC. • No external components on PWM1/CRC disables the CRC. In order to configure the CRC, the follow conditions have to be full filled: • Init Mode (from power-up) or Restart Mode • VCC1>Vrtx • POR=1 • RSTN = LOW The configuration selection is done during the reset delay time tRD1 with a continuous filter time of tCFG_F and the configuration (depending on the voltage level at PWM1/CRC) is latched at the rising edge of RSTN. Figure 4 CRC configuration Selection Timing Diagram at the device power-up. In case of mismatch between CRC setting between the device and µC (CRC_STAT), the device can accept two recovery SPI commands (static patterns). The pattern 67AA AA0EH (addr + rw_bit = 67 ; data = AAAA ; CRC = 0E ) enables the CRC. The pattern E7AA AAC3H (addr + rw_bit = E7 ; data = AAAA ; CRC = C3) disables the CRC. The patterns shall be send only in Normal Mode. For additional details about the CRC setting and configuration, refer also to Chapter 11.3.1. t VCC1 t RSTN t VS_INT VPOR,r tRD1 VRT1,r tCFG_F Configuration selection monitoring period Continuous Filtering with |
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