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TLE9185QXV33 Datasheet(PDF) 17 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 17 Page - Infineon Technologies AG |
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17 / 192 page  TLE9185QXV33 BLDC Driver System Features Datasheet 17 Rev.1.0 2021-01-21 5.2 Device Configuration Two features on the BLDC Driver can be configured by hardware: • The selection of the normal device operation or the Software Development Mode. • Enabling/disabling the CRC on the SPI interface. The configurations are done monitoring the follow pins: •INTN/TEST •PWM1/CRC The hardware configuration can be done typically at device power-up, where the device is in Init Mode or (only in case of CRC setting) in Restart Mode. Software development Mode configuration detail After the RSTN is released, the INTN/TEST pin is internally pulled HIGH with a weak pull-up resistor. Therefore the default configuration is the device in normal operation. In order to configure the Software Development Mode, the following conditions have to be fulfilled: • Init Mode from power-up • VCC1>Vrtx • POR=1 •RSTN = HIGH The Software Development Mode is configured using the following scheme: • Only one external pull-down on INTN/TEST pin followed by an arbitrary SPI command, the device latches the Software Development Mode. • External pull-up or no pull-down on INTN/TEST pin enable the device in normal operation. • To enter Software Development Mode, a pull-down resistor to GND might be used. Figure 3 Software Development Mode Selection Timing Intn_filt is a filtered signal from INTN/TEST, with the filter time tSMD_F (P_11.2.7). Intn_filt starts (at the rising edge if RSNT) wit the value 1. The INTN/TEST is externally pulled-down Soft. Dev. Mode OFF for tSDM_F to avoid supply glitches Soft. Dev. Mode ON LATCHED (first SPI frame) Init Mode Normal Mode Successful latched Software Development Mode Time/us tSDM_F Intn_filt Mode RSTN INTN/TEST Intn_filt: internal filtered INTN/TEST signal Entry in Software Development Mode (not latched ) |
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