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TLE9185QXV33 Datasheet(PDF) 95 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 95 Page - Infineon Technologies AG |
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95 / 192 page  TLE9185QXV33 BLDC Driver Supervision Functions Datasheet 95 Rev.1.0 2021-01-21 10.2.4 Watchdog during Stop Mode The watchdog can be disabled for Stop Mode in Normal Mode. For safety reasons, there is a special sequence to be followed in order to disable the watchdog as described in Figure 49. Two different SPI bits (WD_STM_EN_0, WD_STM_EN_1) in the registers HW_CTRL and WD_CTRL need to be set. Figure 49 Watchdog disabling sequence in Stop Mode If a sequence error occurs, then the bit WD_STM_EN_1 will be cleared and the sequence has to be started again. The watchdog can be enabled by triggering the watchdog in Stop Mode or by switching back to Normal Mode via SPI command. In both cases the watchdog will start with a long open window and the bits WD_STM_EN_1 and WD_STM_EN_0 are cleared. After the long open window the watchdog has to be served as configured in the WD_CTRL register. Note: The bit WD_STM_EN_0 will be cleared automatically when the sequence is started and it was 1 before. WD_STM_EN_0 can also not be set if WD_STM_EN_1 isn't yet set. Correct WD disabling sequence Set bit WD_STM_EN_1 = 1 Set bit WD_STM_EN_0 = 1 with next WD Trigger WD is switched off Sequence Errors Missing to set bit WD_STM_EN_0 with the next watchdog trigger after having set WD_STM_EN_1 Staying in Normal Mode instead of going to Stop Mode with the next trigger Change to Stop Mode Before subsequent WD Trigger Will enable the WD: Switching back to Normal Mode Triggering the watchdog |
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