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TLE9185QXV33 Datasheet(PDF) 71 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 71 Page - Infineon Technologies AG |
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71 / 192 page  Datasheet 71 Rev. 1.0 2021-01-21 TLE9185QXV33 BLDC Driver Gate Drivers Figure 41 Turn-off of an active MOSFET in PWM mode with active gate control, HS as active MOSFET, LS as FW MOSFET. two PWM inputs per half-bridge, active gate control enabled. PWM_NB=1. 9.3.5 Status bits for regulation of turn-on and turn-off delay times The control bits TDREGx (TDREG) indicate if tDONx and tDOFFx of the half-bridge x, using the adaptive control scheme (AGC = 10B or 11B), are in regulation. tFALLx t t t t t tDOFFx VSHL VSHH - IDCHGx - IHOLD Discharge phase Hard off t tPWM_SYNCH tPDCHGx t IHOLD tFVDS tHBxBLANK FW t VGS_HSx VSHx VSHL VSHH IDS_HSDx IPHASE VS HSx internal drive signal - IHOLD IHOLD 0 - IPREDCHGx - IDCHGx - IHARDOFF LSx internal drive signal - IHOLD IHOLD ICHGFWx - IHOLD tOFF timeout Active tHBxCCP Active Synchronized HSx PWM signal Synchronized LSx PWM signal External HSx PWM signal VSHx < VSHL right before the activation of HSx HSx detected as active MOSFET |
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