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TLE9185QXV33 Datasheet(PDF) 70 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 70 Page - Infineon Technologies AG |
70 / 192 page Datasheet 70 Rev. 1.0 2021-01-21 TLE9185QXV33 BLDC Driver Gate Drivers Figure 41 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the active MOSFET (high-side MOSFET in this case) followed by the activation of the FW MOSFET low-side MOSFET in this case) with PWM_NB = 1, AGC[1:0] = 01B or 10B, POCHGDIS = 0 (post-charge enabled). This control scheme is applicable for the following cases: 1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10B (HS MOSFET is considered as active MOSFET by default). 2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET; HBxMODE[1:0] = 01B or 10B. Note: If the synchronized LS PWM rising edge occurs before the end of tHBxCCP active, then the device prevents an activation of the LS MOSFET until tHBxCCP active elapses. In other words, the LS PWM rising edge is ignored until the end of tHBxCCP active. |
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