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TLE9185QXV33 Datasheet(PDF) 67 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 67 Page - Infineon Technologies AG |
67 / 192 page ![]() Datasheet 67 Rev. 1.0 2021-01-21 TLE9185QXV33 BLDC Driver Gate Drivers Figure 40 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the FW MOSFET (low-side MOSFET in this case) followed by the activation of the active MOSFET (high-side MOSFET in this case)1) with PWM_NB = 1, AGC[1:0]=01B or 10B, POCHGDIS = 0 (post-charge enabled). This control scheme is applicable for the following cases: Table 21 PWM Control of HS1 and LS1, PWM_NB = 1, HB1_PWM_EN = 1 HB1MODE[1:0] PWM1/CRC PWM2 HS1 LS1 01 Low Low OFF OFF 01 Low High ON OFF 01 High Low OFF ON 01 High High OFF OFF 10 Low Low OFF OFF 10 Low High OFF ON 10 High Low ON OFF 10 High High OFF OFF Table 22 PWM Control of HS2 and LS2, PWM_NB = 1, HB2_PWM_EN = 1 HB2MODE[1:0] PWM3 PWM4 HS2 LS2 01 Low Low OFF OFF 01 Low High ON OFF 01 High Low OFF ON 01 High High OFF OFF 10 Low Low OFF OFF 10 Low High OFF ON 10 High Low ON OFF 10 High High OFF OFF Table 23 PWM Control of HS3 and LS3, PWM_NB = 1, HB3_PWM_EN = 1 HB3MODE[1:0] PWM5 PWM6 HS3 LS3 01 Low Low OFF OFF 01 Low High ON OFF 01 High Low OFF ON 01 High High OFF OFF 10 Low Low OFF OFF 10 Low High OFF ON 10 High Low ON OFF 10 High High OFF OFF 1) If the synchronized HS PWM rising edge occurs after tHBxCCP FW and before the end of tOFF timeout FW, then the LS MOSFET is discharged with IHARDOFF and the HS is turned on, when the HS PWM rising edge is detected |
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