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TLE9185QXV33 Datasheet(PDF) 62 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 62 Page - Infineon Technologies AG |
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62 / 192 page  Datasheet 62 Rev. 1.0 2021-01-21 TLE9185QXV33 BLDC Driver Gate Drivers Figure 37 PWM falling edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0. 9.3.3.3 Time modulation of pre-charge and pre-discharge times If DEEP_ADAP =0: VSHx VSHL VSHH IGS_LSx IGS_HSx IPRECHGx ICHGMAXx ICHGx VGS_LSx tDONx tRISEx Postcharge Phase VSHL 0 t t t t tPCHGx t IDS_LSDx tHBxBLANK Active VS IPRECHGx LSx internal drive signal t - IHOLD IHOLD 0 ICHGMAXx ICHGx IHOLD HSx internal drive signal - IHARDOFF - IHOLD t Hard off - IHOLD Charge phase tFVDS tFVDS ICHGx VSHH Synchronized intern. PWMz External PWMz tPWM_SYNCH t t IPHASE Detection of the active MOSFET (EN_GEN_CHECK= 1). VSH > VSHH: LS MOSFET is the active MOSFET |
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