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TLE9185QXV33 Datasheet(PDF) 40 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 40 Page - Infineon Technologies AG |
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40 / 192 page  TLE9185QXV33 BLDC Driver Interrupt Function Datasheet 40 Rev.1.0 2021-01-21 Note: During Restart Mode the SPI is blocked and the microcontroller is in reset. Therefore the INTN will not be in Restart Mode, which is the same behavior in Fail-Safe Mode or Sleep Mode. In addition to this behavior, INTN will be triggered when Stop Mode is entered and not all wake source bits were cleared in the WK_STAT register and also the LSx_DSOV_BRK bits in the DSOV register.. The SPI status registers are updated at every falling edge of the INTN pulse. All interrupt events are stored in the respective register until the register is cleared via SPI command. A second SPI read after reading out the respective status register is optional but recommended to verify that the interrupt event is not present anymore. The interrupt behavior is shown in Figure 20. The INTN pin is also used during Init Mode to select the Software Development Mode entry. See Chapter 5.2 for further information. In case of pending INTN event (SPI Status registers are not cleared after INTN event), additional periodical INTN events are generated as shown in Figure 21. The periodical INTN events generation can be disabled via SPI command using INTN_CYC_EN bit. Figure 20 Interrupt Signalization Behavior Note: For two or more interrupt events at the same time, when INTN pin is low the same time, it will not start multiple toggling. INTN WKx tINTN tINTD Update of WK_STAT register SPI Read & Clear Update of WK_STAT register WK_STAT contents WKx no WK no WK optional SPI Read & Clear WK_STAT contents WKx no WK No SPI Read & Clear Command sent |
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