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TLE9185QXV33 Datasheet(PDF) 39 Page - Infineon Technologies AG |
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TLE9185QXV33 Datasheet(HTML) 39 Page - Infineon Technologies AG |
39 / 192 page ![]() TLE9185QXV33 BLDC Driver Interrupt Function Datasheet 39 Rev.1.0 2021-01-21 8 Interrupt Function 8.1 Block and Functional Description Figure 19 Interrupt Block Diagram The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is designed as a push/pull output stage as shown in Figure 19. An interrupt is triggered and the INTN pin is pulled low (active low) for tINTN in Normal Mode and Stop Mode and it is released again once tINTN is expired. The minimum high-time of INTN between two consecutive interrupts is tINTND. An interrupt does not cause a device mode change. Two different interrupt generation methods are implemented: • Interrupt Mask: One dedicated register (INT_MASK) is intended to enable or disable set of interrupt sources. The interrupt sources follow the SPI Status Information Field. In details: – SUPPLY_STAT: “OR” of all bits on SUP_STAT register except POR, VCC1_UV, VCC1_SC, VCC1_OV – TEMP_STAT: “OR” of all bits on THERM_STAT register except TSD2 – BD_STAT: “OR” of all bits on DSOV register – SPI_CRC_FAIL: or between SPI_FAIL and CRC_FAIL bits on DEV_STAT register. • Wake-up events: all wake-up events stored in the wake status SPI register WK_STAT only in case the corresponding input was configured as wake-up source. The wake-up sources are: –via WK pin – via TIMERx (cyclic wake) – via LSx_DSOV_BRK if any of the brake-feature is enabled The methods are both available at the same time. Note: The errors which will cause Restart or Fail-Safe Mode (VCC1_UV, VCC1_SC, VCC1_OV, TSD2) are the exceptions of an INTN generation. Also the bit POR will not generate interrupts. If the above mentioned bits are not cleared after the device is back in Normal Mode or Stop Mode, the INTN is periodically generated (Register based cyclic interrupt generation). Note: Periodical interrupts are only generated by CRC fail and SPI fail from DEV_STAT register. INTERRUPT BLOCK.VSD Interrupt logic INTN Time out Vcc1 |
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