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LTC6754 Datasheet(PDF) 17 Page - Analog Devices |
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LTC6754 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 34 page  LTC6563 17 Rev. 0 For more information www.analog.com PIN FUNCTIONS GND (Pins 1, 3, 18, 20, Exposed Pad Pin 25): Negative Power Supply. Normally tied to ground. All GND pins and the exposed pad must be tied to the same voltage. The exposed pad (pin 25) should have multiple via holes to the underlying ground plane for low inductance and good heat transfer. IN4, IN1, IN2, IN3 (Pin 2, Pin 19, Pin 21, Pin 24,): Input pins for the transimpedance amplifier for channels 4, 1, 2, and 3 respectively. The active channel is internally biased to 0.8V. See the Applications Information section for spe- cific recommendation. PWRMD (Pin 4): Power mode is a CMOS input for con- trolling the power consumption. The PWRMD pin has a 208k internal pull-up resistor to VCCI. Default value is 3.3V. VCCI (Pin 5): Positive power supply for the input stages. Typically, 3.3V. A series ferrite bead such as the MPZ1005A331ETD25 should be used and bypass capaci- tor of 680pF and 0.1µF should be placed as close to the part as possible between VCCI and ground. OMUX (Pin 6): Output MUX is a CMOS input for con- trolling the output multiplexing function. The OMUX pin has internal 208k pull-up resistor to VCCI. Default value is 3.3V. CM (Pin 7): Output Common Mode Reference Voltage. The voltage on this pin sets the output common mode voltage level. On a 3.3V supply, the CM pin floats to a default 0.9V. The CM pin has an input impedance of 16.3kΩ. The CM pin should be bypassed with a high- quality ceramic capacitor of at least 0.01µF. HI (Pin 8): High Side Clamp Voltage. The voltage applied to the HI pin sets the upper voltage limit to OUT and OUT pins. The HI voltage also limits the lower voltage swing on both output pins to 2VCM – HI, for symmetrical clamping around the CM voltage. On a 3.3V supply, the HI pin will float to a default 1.8V. The HI pin has an input impedance of 13.6kΩ. The HI pin should be bypassed with a high- quality ceramic capacitor of at least 0.01µF. OUT, OUT (Pin 9, Pin 12): Differential Output Pins. For voltage mode output, connect OUT to TERM and OUT to TERM. For current mode output or when using external load resistors, float TERM and TERM. TERM, TERM (Pin 10, Pin 11): Internal Termination. These pins have 50Ω load resistors coupled to GND and are intended to connect to the differential output pins. CHSEL1, CHSEL0 (Pin 13, Pin 15): MSB and LSB for Channel Selection. These pins are CMOS inputs with inter- nal 218k pull-down resistors to GND. VCCO (Pin 14): Positive power supply for the output stage. Typically, 3.3V. VCCO can be tied to VCCI for sin- gle supply operation. A series ferrite bead such as the MPZ1005A331ETD25 should be used and bypass capaci- tors of 680pF and 0.1µF should be placed as close as possible between VCCO and ground. OFFSET (Pin 16): Input Offset Adjust. This pin accepts a voltage input that controls current sources on each input pin. These current sources can be used to cancel DC cur- rents flowing into the detector. The OFFSET pin has an internal pull-down resistor to GND. TILT (Pin 17): Output Differential Offset. The voltage on this pin controls the outputs’ differential offset. The TILT pin has an internal 22.7k pull-down resistor to GND. ADJ0, ADJ1 (Pin 22, Pin 23): LSB and MSB for output gain and current adjusts. The adjust pins set the output stage quiescent current and current gain. See Applications Information section to optimize the ADC interface. These pins are CMOS inputs with internal 218k pull-down resis- tors to GND. |
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