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MAX14850AEE+T Datasheet(PDF) 2 Page - Maxim Integrated Products |
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MAX14850AEE+T Datasheet(HTML) 2 Page - Maxim Integrated Products |
2 / 17 page VCCA to GNDA........................................................-0.3V to +6V VCCB to GNDB........................................................-0.3V to +6V OUTA1, OUTA2 to GNDA....................... -0.3V to (VCCA + 0.3V) OUTB1, OUTB2 to GNDB...................... -0.3V to (VCCB + 0.3V) INA1, INA2, I/OA1, I/OA2 to GNDA ........................-0.3V to +6V INB1, INB2, I/OB1, I/OB2 to GNDB ........................-0.3V to +6V Short-Circuit Duration (OUTA_ to GNDA or VCCA, OUTB_ to GNDB or VCCB) ........................Continuous Continuous Current (I/OA_, I/OB_) Pin............................±50mA Continuous Power Dissipation (TA = +70°C) SOIC (derate 13.3mW/°C above +70°C)...................1067mW QSOP (derate 9.6mW/°C above +70°C)..................771.5mW Operating Temperature Range......................... -40°C to +125°C Junction Temperature......................................................+150°C Storage Temperature Range............................ -65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow).......................................+260°C Package Code S16+3 Outline Number 21-0041 Land Pattern Number 90-0097 THERMAL RESISTANCE, MULTILAYER BOARD Junction to Ambient (θJA) 75°C/W Junction to Case (θJC) 24°C/W Package Code E16+1 Outline Number 21-0055 Land Pattern Number 90-0167 THERMAL RESISTANCE, MULTILAYER BOARD Junction to Ambient (θJA) 103.7°C/W Junction to Case (θJC) 37°C/W 16 SOIC 16 QSOP Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package Information MAX14850 Six-Channel Digital Isolator www.maximintegrated.com Maxim Integrated │ 2 |
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