PRELIMINARY

2Mb (128K x 16) Pseudo Static RAM

CG6263AM

Weida Semiconductor, Inc.

38-XXXXX

Revised Feb 2004

Features

• Wide voltage range: 2.70V–3.30V

• Access Time: 70ns

• Ultra-low active power

— Typical active current: 2.0mA @ f = 1 MHz

• Ultra low standby power

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Offered in a 48 Ball BGA Package

Functional Description[1]

The CG6263AM is a high-performance CMOS Pseudo static

RAM organized as 128K words by 16 bits that supports an

asynchronous

memory

interface.

This

device

features

advanced circuit design to provide ultra-low active current.

portable applications such as cellular telephones. The device

can be put into standby mode reducing power consumption by

more than 99% The device can also be put into standby mode

when deselected (CE HIGH or both BHE and BLE are HIGH).

high-impedance state when: deselected (CE HIGH ), outputs

are disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH), or during a write

operation (CE LOW and WE LOW). The addresses must not

be toggled once the read is started on the device.

Writing to the device is accomplished by taking Chip Enables

(CE LOW ) and Write Enable (WE) input LOW. If Byte Low

Reading from the device is accomplished by taking Chip

Enables (CE LOW) and Output Enable (OE) LOW while

forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)

is LOW, then data from the memory location specified by the

complete description of read and write modes

Note:

1.

For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

128K × 16

RAM Array

I/O0 – I/O7

COLUMN DECODER

DATA IN DRIVERS

OE

I/O8 – I/O15

WE

BLE

BHE

Power- Down

Circuit

BHE

BLE

CE

CE