CYNSE70032
Document #: 38-02042 Rev. *E
Page 3 of 126
TABLE OF CONTENTS (continued)
14.0 DEPTH-CASCADING .................................................................................................................. 96
14.1 Depth-Cascading up to Eight Devices (One Block) ............................................................... 96
14.2 Depth-Cascading up to 31 Devices (Four Blocks) ................................................................. 97
14.3 Depth-Cascading for a FULL Signal ...................................................................................... 97
15.0 SRAM ADDRESSING ................................................................................................................. 98
15.1 Generating an SRAM BUS Address ...................................................................................... 99
15.2 SRAM PIO Access ................................................................................................................. 99
15.3 SRAM Read with a Table of One Device ............................................................................... 99
15.4 SRAM Read with a Table of up to Eight Devices ................................................................. 100
15.5 SRAM Read with a Table of up to 31 Devices ..................................................................... 103
15.6 SRAM Write with a Table of One Device ............................................................................. 106
15.7 SRAM Write with a Table of up to Eight Devices ................................................................. 107
15.8 SRAM Write with Table(s) Consisting of up to 31 Devices .................................................. 110
16.0 POWER ..................................................................................................................................... 114
16.1 The Proper Power-up Sequence ......................................................................................... 114
17.0 APPLICATION .......................................................................................................................... 114
18.0 JTAG (1149.1) TESTING .......................................................................................................... 115
19.0 ELECTRICAL SPECIFICATIONS ............................................................................................. 116
20.0 AC TIMING WAVEFORMS ....................................................................................................... 117
21.0 PINOUT DESCRIPTIONS AND PACKAGE DIAGRAMS ......................................................... 120
22.0 ORDERING INFORMATION ..................................................................................................... 124
23.0 PACKAGE DIAGRAMS ............................................................................................................ 124
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