CYNSE70032
Document #: 38-02042 Rev. *E
Page 99 of 126
15.1
Generating an SRAM BUS Address
Table 15-1 details SRAM bus address generation.
15.2
SRAM PIO Access
The remainder of Section 15.0 describes SRAM Read and SRAM Write operations.
SRAM Read enables Read access to the off-chip SRAM that contains associative data. The latency from the issuance of the
Read instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read
instruction is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed into the
configuration register. Note. SRAM Read is a blocking operation—no new instruction can begin until the ACK is returned by the
selected device performing the access.
SRAM Write enables Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed into the device configuration register. Note. SRAM Write is a pipelined operation—new
instruction can begin right after the previous command has ended.
15.3
SRAM Read with a Table of One Device
SRAM Read enables Read access to the off-chip SRAM that contains associative data. The latency from the issuance of the
Read instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend
on the TLSZ value parameter programmed into the device configuration register. The latency of the ACK from the Read instruction
is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed into the configuration
register. The following explains the SRAM Read operation in a table with only one device and having the following parameters:
TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 15-1 shows the associated timing diagram. For the following
description, the selected device refers only to the device in the table because it is the only device to be accessed.
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[21:19] on CMD[8:6].
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0] and drives ACK from High-Z to LOW.
• Cycle 5: The selected device drives the Read address on SADR[21:0]; it also drives ACK HIGH, CE_L LOW, and ALE_L LOW.
• Cycle 6: The selected device drives CE_L HIGH, ALE_L HIGH, the SADR bus, the DQ bus in a three-state condition, and
ACK LOW.
At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin.
Table 15-1. SRAM Bus Address
Command
SRAM Operation
21
20
19
[18:14]
[13:0]
Search
Read
C8
C7
C6
ID[4:0]
Index[13:0]
Learn
Write
C8
C7
C6
ID[4:0]
NFA[13:0]
PIO Read
Read
C8
C7
C6
ID[4:0]
ADR13:0]
PIO Write
Write
C8
C7
C6
ID[4:0]
ADR[13:0]
Indirect Access
Write/Read
C8
C7
C6
ID[4:0]
SSR[13:0]
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