CYNSE70032
Document #: 38-02042 Rev. *E
Page 9 of 126
1.0
Overview
Cypress Semiconductor Corporation’s (Cypress’s) CYNSE70032 network search engine (NSE) incorporates patent-pending
Associative Processing Technology™ (APT) and is designed to be a high-performance, pipelined, synchronous, 16K-entry NSE.
The CYNSE70032 database entry size can be 68, 136, or 272 bits. In the 68-bit entry mode, the size of the database is 16K
entries. In the 136-bit mode, the size of the database is 8K entries, and in the 272-bit mode, the size of the database is 4K entries.
The CYNSE70032 is configurable to support multiple databases with different entry sizes. The 36-bit entry table can be imple-
mented using the global mask registers (GMRs) building-database size of 32K entries with a single device.
The search engine can sustain 83 million transactions per second when the database is programmed or configured as 68 or 136
bits. When the database is programmed to have an entry size of 34 or 272 bits, the search engine will perform at 41.5 million
transactions per second. The CYNSE70032 can be used to accelerate network protocols such as longest-prefix match (CIDR),
address-resolution protocol (ARP), multiprotocol label switching (MPLS), and other layer 2, 3, and 4 protocols.
This high-speed, high-capacity NSE can be deployed in a variety of networking and communications applications. The perfor-
mance and features of the CYNSE70032 device make it attractive in applications such as Enterprise local-area network (LAN)
switches and routers and broadband switching and/or routing equipment supporting multiple data rates at OC-48 and beyond.
The NSE is designed to be scalable in order to support network database sizes of up to 992K entries specifically for environments
that require large network policy databases. The block diagram for the CYNSE70032 device is shown on page 10.
2.0
CYNSE70032 Features
• 32K 34-bit entries in a single device
• 16K entries in 68-bit mode, 8K entries in 136-bit mode, 4K entries in 272-bit mode
• 83 million transactions per second in 68- and 136-bit configurations
• 41.5 million transactions in 34- and 272-bit configurations
• Searches any subfield in a single cycle
• Synchronous pipelined operation
• Up to 31 NSEs can be cascaded
• When cascaded, the database entries can range to 992K 36-bit entries
• Multiple width tables in a single database bank
• Glueless interface to industry standard SRAMs and/or SSRAMs
• Simple hardware instruction interface
• IEEE 1149.1 test access port
• 1.8V core voltage supply
• 2.5/3.3V I/O voltage supply
• 272-pin BGA package.
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